1. Field of the Invention
This invention relates to the field of computer processors, and more particularly to computer processors executing variable-length instructions.
2. Description of the Related Art
Computer processor architectures may generally be classified as either complex instruction set computing (CISC) architectures or reduced instruction set computing (RISC) architectures. CISC architectures (e.g., the xc3x9786 processor architecture) specify an instruction set including high level, relatively complex instructions. Often, processors implementing CISC architectures decompose the complex instructions into multiple simpler operations which may be more readily implemented in hardware. Microcoded routines stored in an on-chip read-only memory (ROM) have been successfully employed for providing the decomposed operations corresponding to an instruction. More recently, hardware decoders which separate the complex instructions into simpler operations have been adopted by certain CISC processor designers.
Conversely, RISC architectures specify an instruction set including low level, relatively simple instructions. Typically, each instruction within the instruction set is directly implemented in hardware. Complexities associated with the CISC approach are removed, resulting in simpler hardware implementations. Such simpler hardware implementations are often capable of higher frequency operation. The MIPS architecture is an exemplary RISC architecture.
Although not necessarily a defining feature, variable-length instruction sets have often been associated with CISC architectures, while fixed-length instruction sets have been associated with RISC architectures. Variable-length instruction sets use dissimilar numbers of bits to encode the various instructions within the set as well as to specify addressing modes for the instructions, etc. Generally speaking, variable-length instruction sets attempt to pack instruction information as efficiently as possible into the byte or bytes representing each instruction. Conversely, fixed-length instruction sets employ the same number of bits for each instruction (the number of bits is typically a multiple of eight such that each instruction fully occupies a fixed number of bytes). Typically, a small number of instruction formats including fixed fields of information are defined. Decoding each instruction is thereby simplified to routing bits corresponding to each fixed field to logic designed to decode that field.
Because each instruction in a fixed-length instruction set includes a fixed number of bytes, locating instructions is simplified as well. The location of numerous instructions subsequent to a particular instruction is implied by the location of the particular instruction (i.e. as fixed offsets from the location of the particular instruction). Conversely, locating a second variable-length instruction requires locating the end of the first variable-length instruction; locating a third variable-length instruction requires locating the end of the second variable-length instruction, etc. Still further, variable-length instructions lack the fixed field structure of fixed-length instructions. Decoding is further complicated by the lack of fixed fields.
RISC architectures employing fixed-length instruction sets suffer from problems not generally applicable to CISC architectures employing variable-length instruction sets. Because each instruction is fixed length, certain of the simplest instructions may effectively waste memory by occupying bytes which do not convey information concerning the instruction. In contrast, variable-length instruction sets pack the instruction information into a minimal number of bytes.
Still further, since RISC architectures do not include the more complex instructions employed by CISC architectures, the number of instructions in a program coded with RISC instructions may be larger than the number of instructions employed in the same program coded in with CISC instructions. Each of the more complex instructions coded in the CISC version of the program is replaced by multiple instructions in the RISC version of the program. Therefore, the RISC version of a program often occupies significantly more memory than the CISC version of the program. Correspondingly, a greater instruction bandwidth is required between memory storing the program and the processor is needed for the RISC version of the program than for the CISC version of the program.
In the past, the MIPS RISC architecture supported only a 32-bit MIPS instruction set including fixed-length, 32-bit MIPS instructions. More recently, the MIPS architecture has been expanded to include an optional xe2x80x9cMIPS16 application-specific extension (ASE).xe2x80x9d The MIPS16 ASE defines both 16-bit MIPS16 instructions and 32-bit MIPS16 instructions. The MIPS16 instruction set is thus by definition a variable-length instruction set. Each xe2x80x9ccompressedxe2x80x9d MIPS16 instruction has a corresponding xe2x80x9cnon-compressedxe2x80x9d 32-bit MIPS instruction, and translation hardware is commonly used to translate MIPS16 instructions to corresponding 32-bit MIPS instructions for execution by a MIPS processor. The MIPS16 instruction set allows instructions to be encoded using fewer bits, and the MIPS16 version of a program often occupies significantly less memory than the 32-bit MIPS version of the same program.
An apparatus and method for translating variable-length instructions to fixed-length instructions are described. The apparatus (e.g., an instruction decompressor) includes instruction decompression logic and caching logic. The instruction decompression logic receives a first portion of an instruction data block, an output signal produced by the caching logic, and a control signal during a time period (e.g., a cycle of a clock signal). The instruction data block may include, for example, a fixed number of bits of software code (i.e., instruction data). The instruction data block includes a first variable-length instruction. The instruction decompression logic produces a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal produced by the caching logic, and the control signal.
The caching logic includes a storage unit. During the same time period that the instruction decompression logic produces the fixed-length instruction, the caching logic receives a second portion of the instruction data block and the control signal. The caching logic stores the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal. During the time period, the output signal produced by the caching logic is either the second portion of the instruction data block or the contents of the storage unit.
In one embodiment, the apparatus is an instruction decompressor receiving 32-bit blocks of instruction data (e.g., from an instruction cache). Each 32-bit instruction data block includes at least one, and at most two, variable-length MIPS16 instructions. During a cycle of a provided clock signal, the instruction decompressor may translate (i.e., decompress) a complete first MIPS16 instruction within a first 16-bit portion of the 32-bit instruction data block to form a fixed-length, 32-bit MIPS instruction. When the second 16-bit portion of the 32-bit instruction data block includes only a portion of a second MIPS16 instruction, the caching logic is used to save information conveyed by the portion of the second MIPS16 instruction for use during the next cycle of the clock signal. By virtue of the caching logic, the instruction decompressor is able to produce a 32-bit MIPS instruction during each cycle of the clock signal.
The storage unit of the apparatus may, for example, store the second portion of the instruction data block during the time period when the control signal indicates the instruction data block includes only a portion of a second variable-length instruction. The apparatus may include check logic receiving the instruction data block and producing the control signal dependent upon whether or not the instruction data block includes only a portion of a second variable-length instruction. The apparatus may also include routing logic receiving the instruction data block and producing the first and second portions of the instruction data block.
One embodiment of a method for translating variable-length instructions to fixed-length instructions includes receiving the above described instruction data block. The following steps are performed simultaneously: (i) translating the first variable-length instruction to produce a fixed-length instruction; and (ii) if the instruction data block includes only a portion of a second variable-length instruction, saving at least a part of the portion of the second variable-length instruction for use in subsequent translating of the second variable-length instruction. The portion of the second variable-length instruction may, for example, include information identifying the instruction type (e.g., opcode information) and instruction data. In this situation, the saving may include: (i) saving a value of a control signal indicating the instruction type; and (ii) saving at least a part of the instruction data.
A central processing unit is described including the instruction decompressor, and a computer system is described including the central processing unit.